58 static uint8_t spi_current_config = 0xFF;
70 static uint8_t cs_bcd[8] = {
72 (0xFF & (0 << MSPI_CS_PIN_0) & (0 << MSPI_CS_PIN_1) & (0 << MSPI_CS_PIN_2)),
74 (0x00 | (1 << MSPI_CS_PIN_0) | (0 << MSPI_CS_PIN_1) | (0 << MSPI_CS_PIN_2)),
75 (0x00 | (0 << MSPI_CS_PIN_0) | (1 << MSPI_CS_PIN_1) | (0 << MSPI_CS_PIN_2)),
76 (0x00 | (1 << MSPI_CS_PIN_0) | (1 << MSPI_CS_PIN_1) | (0 << MSPI_CS_PIN_2)),
77 (0x00 | (0 << MSPI_CS_PIN_0) | (0 << MSPI_CS_PIN_1) | (1 << MSPI_CS_PIN_2)),
78 (0x00 | (1 << MSPI_CS_PIN_0) | (0 << MSPI_CS_PIN_1) | (1 << MSPI_CS_PIN_2)),
79 (0x00 | (0 << MSPI_CS_PIN_0) | (1 << MSPI_CS_PIN_1) | (1 << MSPI_CS_PIN_2)),
80 (0x00 | (1 << MSPI_CS_PIN_0) | (1 << MSPI_CS_PIN_1) | (1 << MSPI_CS_PIN_2))
84 static usart_t usart_ports[2] = {
107 uint8_t mspi_uart_port = MSPI_USART1;
112 MSPI_CS_PORT_DDR |= (1 << MSPI_CS_PIN_0) | (1 << MSPI_CS_PIN_1) | (1 << MSPI_CS_PIN_2);
113 MSPI_CS_PORT &= ~((1 << MSPI_CS_PIN_0) | (1 << MSPI_CS_PIN_1) | (1 << MSPI_CS_PIN_2));
119 *(usart_ports[mspi_uart_port].UBRRn) = 0;
121 *(usart_ports[mspi_uart_port].XCKn_DDR) |= (1 << usart_ports[mspi_uart_port].XCKn);
123 *(usart_ports[mspi_uart_port].UCSRnC) = ((MSPI_ENABLE) | mode);
125 *(usart_ports[mspi_uart_port].UCSRnB) = ((1 << RXEN0) | (1 << TXEN0));
126 *(usart_ports[mspi_uart_port].UBRRn) = baud;
134 if (spi_current_config != spi_bus_config[cs].checksum) {
137 spi_current_config = spi_bus_config[cs].checksum;
141 MSPI_CS_PORT |= cs_bcd[cs];
148 MSPI_CS_PORT &= ~((1 << MSPI_CS_PIN_0) | (1 << MSPI_CS_PIN_1) | (1 << MSPI_CS_PIN_2));
154 uint8_t receive_data;
159 while (!(*(usart_ports[mspi_uart_port].UCSRnA) & (1 << UDRE0))) {
161 if(cnt > 500)
return 0xFF;
163 *(usart_ports[mspi_uart_port].UDRn) = data;
167 while (!(*(usart_ports[mspi_uart_port].UCSRnA) & (1 << RXC0))) {
169 if(cnt > 500)
return 0xFF;
171 receive_data = *(usart_ports[mspi_uart_port].UDRn);
179 *(usart_ports[mspi_uart_port].UCSRnA) = MSPI_DISABLE;
180 *(usart_ports[mspi_uart_port].UCSRnB) = MSPI_DISABLE;
181 *(usart_ports[mspi_uart_port].UCSRnC) = MSPI_DISABLE;
189 spi_bus_config[cs].dev_mode = mode;
190 spi_bus_config[cs].dev_baud = baud;
191 spi_bus_config[cs].checksum = mode + baud;
198 *(usart_ports[mspi_uart_port].UBRRn) = 0;
200 *(usart_ports[mspi_uart_port].XCKn_DDR) |= (1 << usart_ports[mspi_uart_port].XCKn);
202 *(usart_ports[mspi_uart_port].UCSRnC) = ((MSPI_ENABLE) | new_config.dev_mode);
204 *(usart_ports[mspi_uart_port].UCSRnB) = ((1 << RXEN0) | (1 << TXEN0));
205 *(usart_ports[mspi_uart_port].UBRRn) = new_config.dev_baud;