Contiki-Inga 3.x
uart0.c
1 /*
2  * Copyright (c) 2014, Analog Devices, Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  *
14  * 3. Neither the name of the copyright holder nor the names of its
15  * contributors may be used to endorse or promote products derived
16  * from this software without specific prior written permission.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
22  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
29  * OF THE POSSIBILITY OF SUCH DAMAGE.
30  */
31 /**
32  * \author Maxim Salov <max.salov@gmail.com>, Ian Martin <martini@redwirellc.com>
33  */
34 
35 #include "rl78.h" /* for f_CLK */
36 #include "sfrs.h"
37 #include "sfrs-ext.h"
38 
39 #include "uart0.h"
40 
41 #define DESIRED_BAUDRATE 38400
42 
43 /* Note that only 9600, 38400, and 115200 bps were tested. */
44 #define PRESCALE_THRESH ((38400 + 115200) / 2)
45 #define PRS_VALUE ((DESIRED_BAUDRATE < PRESCALE_THRESH) ? 4 : 0)
46 #define f_MCK (f_CLK / (1 << PRS_VALUE))
47 #define SDR_VALUE (f_MCK / DESIRED_BAUDRATE / 2 - 1)
48 
49 void
50 uart0_init(void)
51 {
52  /* Reference R01AN0459EJ0100 or hardware manual for details */
53  PIOR = 0U; /* Disable IO redirection */
54  PM1 |= 0x06U; /* Set P11 and P12 as inputs */
55  SAU0EN = 1; /* Supply clock to serial array unit 0 */
56  SPS0 = (PRS_VALUE << 4) | PRS_VALUE; /* Set input clock (CK00 and CK01) to fclk/16 = 2MHz */
57  ST0 = 0x03U; /* Stop operation of channel 0 and 1 */
58  /* Setup interrupts (disable) */
59  STMK0 = 1; /* Disable INTST0 interrupt */
60  STIF0 = 0; /* Clear INTST0 interrupt request flag */
61  STPR10 = 1; /* Set INTST0 priority: lowest */
62  STPR00 = 1;
63  SRMK0 = 1; /* Disable INTSR0 interrupt */
64  SRIF0 = 0; /* Clear INTSR0 interrupt request flag */
65  SRPR10 = 1; /* Set INTSR0 priority: lowest */
66  SRPR00 = 1;
67  SREMK0 = 1; /* Disable INTSRE0 interrupt */
68  SREIF0 = 0; /* Clear INTSRE0 interrupt request flag */
69  SREPR10 = 1; /* Set INTSRE0 priority: lowest */
70  SREPR00 = 1;
71  /* Setup operation mode for transmitter (channel 0) */
72  SMR00 = 0x0023U; /* Operation clock : CK00,
73  Transfer clock : division of CK00
74  Start trigger : software
75  Detect falling edge as start bit
76  Operation mode : UART
77  Interrupt source : buffer empty
78  */
79  SCR00 = 0x8097U; /* Transmission only
80  Reception error interrupt masked
81  Phase clock : type 1
82  No parity
83  LSB first
84  1 stop bit
85  8-bit data length
86  */
87  SDR00 = SDR_VALUE << 9;
88  /* Setup operation mode for receiver (channel 1) */
89  NFEN0 |= 1; /* Enable noise filter on RxD0 pin */
90  SIR01 = 0x0007U; /* Clear error flags */
91  SMR01 = 0x0122U; /* Operation clock : CK00
92  Transfer clock : division of CK00
93  Start trigger : valid edge on RxD pin
94  Detect falling edge as start bit
95  Operation mode : UART
96  Interrupt source : transfer end
97  */
98  SCR01 = 0x4097U; /* Reception only
99  Reception error interrupt masked
100  Phase clock : type 1
101  No parity
102  LSB first
103  1 stop bit
104  8-bit data length
105  */
106  SDR01 = SDR_VALUE << 9;
107  SO0 |= 1; /* Prepare for use of channel 0 */
108  SOE0 |= 1;
109  P1 |= (1 << 2); /* Set TxD0 high */
110  PM1 &= ~(1 << 2); /* Set output mode for TxD0 */
111  PM1 |= (1 << 1); /* Set input mode for RxD0 */
112  SS0 |= 0x03U; /* Enable UART0 operation (both channels) */
113  STIF0 = 1; /* Set buffer empty interrupt request flag */
114 }
115 void
116 uart0_putchar(int c)
117 {
118  while(0 == STIF0) ;
119  STIF0 = 0;
120  SDR00 = c;
121 }
122 char
123 uart0_getchar(void)
124 {
125  char c;
126  while(!uart0_can_getchar()) ;
127  c = SDR01;
128  SRIF0 = 0;
129  return c;
130 }
131 int
132 uart0_puts(const char *s)
133 {
134  int len = 0;
135  SMR00 |= 0x0001U; /* Set buffer empty interrupt */
136  while('\0' != *s) {
137  uart0_putchar(*s);
138  s++;
139  ++len;
140  }
141 #if 0
142  while(0 == STIF0) ;
143  STIF0 = 0;
144  SDR00.sdr00 = '\r';
145 #endif
146  SMR00 &= ~0x0001U;
147  uart0_putchar('\n');
148 #if 0
149  while(0 != SSR00.BIT.bit6) ; /* Wait until TSF00 == 0 */
150 #endif
151  return len;
152 }
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