Contiki-Inga 3.x
rtimer-arch.c
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1 /*
2  * Copyright (c) 2007, Swedish Institute of Computer Science.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
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8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the Institute nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * This file is part of the Contiki operating system.
30  *
31  */
32 
33 /**
34  * \file
35  * AVR-specific rtimer code
36  * Defaults to Timer3 for those ATMEGAs that have it.
37  * If Timer3 not present Timer1 will be used.
38  * \author
39  * Fredrik Osterlind <fros@sics.se>
40  * Joakim Eriksson <joakime@sics.se>
41  */
42 
43 /* OBS: 8 seconds maximum time! */
44 
45 #include <avr/io.h>
46 
47 #include <avr/interrupt.h>
48 #include <stdio.h>
49 
50 #include "sys/energest.h"
51 #include "sys/rtimer.h"
52 #include "rtimer-arch.h"
53 
54 #if defined(__AVR_ATmega1284P__)
55 #define ETIMSK TIMSK3
56 #define ETIFR TIFR3
57 #define TICIE3 ICIE3
58 
59 //Has no 'C', so we just set it to B. The code doesn't really use C so this
60 //is safe to do but lets it compile. Probably should enable the warning if
61 //it is ever used on other platforms.
62 //#warning no OCIE3C in timer3 architecture, hopefully it won't be needed!
63 
64 #define OCIE3C OCIE3B
65 #define OCF3C OCF3B
66 #endif // 1281 / 1284p
67 
68 #if defined(__AVR_ATmega1281__) || defined(__AVR_AT90USB1287__) || defined(__AVR_ATmega128RFA1__)
69 #define ETIMSK TIMSK3
70 #define ETIFR TIFR3
71 #define TICIE3 ICIE3
72 #endif // atusb
73 
74 #if defined(__AVR_ATmega328P__) || defined(__AVR_ATmega644__)
75 #define TIMSK TIMSK1
76 #define TICIE1 ICIE1
77 #define TIFR TIFR1
78 #endif // 328p / 644
79 
80 /* Track flow through rtimer interrupts*/
81 #if DEBUGFLOWSIZE&&0
82 extern uint8_t debugflowsize,debugflow[DEBUGFLOWSIZE];
83 #define DEBUGFLOW(c) if (debugflowsize<(DEBUGFLOWSIZE-1)) debugflow[debugflowsize++]=c
84 #else
85 #define DEBUGFLOW(c)
86 #endif
87 
88 /*---------------------------------------------------------------------------*/
89 #if defined(__AVR_ATxmega256A3__) || defined(__AVR_ATxmega256A3U__)
90 ISR(RTC_OVF_vect)
91 {
92  rtimer_run_next();
93 }
94 #elif defined(__AVR_ATxmega256A3B__) || defined(__AVR_ATxmega256A3BU__)
95 ISR(RTC32_OVF_vect)
96 {
97  rtimer_run_next();
98 }
99 #elif defined(TCNT3) && RTIMER_ARCH_PRESCALER
100 ISR (TIMER3_COMPA_vect) {
101  DEBUGFLOW('/');
102  ENERGEST_ON(ENERGEST_TYPE_IRQ);
103 
104  /* Disable rtimer interrupts */
105  ETIMSK &= ~((1 << OCIE3A) | (1 << OCIE3B) | (1 << TOIE3) |
106  (1 << TICIE3) | (1 << OCIE3C));
107 
108 #if RTIMER_CONF_NESTED_INTERRUPTS
109  /* Enable nested interrupts. Allows radio interrupt during rtimer interrupt. */
110  /* All interrupts are enabled including recursive rtimer, so use with caution */
111  sei();
112 #endif
113 
114  /* Call rtimer callback */
115  rtimer_run_next();
116 
117  ENERGEST_OFF(ENERGEST_TYPE_IRQ);
118  DEBUGFLOW('\\');
119 }
120 
121 #elif RTIMER_ARCH_PRESCALER
122 #warning "No Timer3 in rtimer-arch.c - using Timer1 instead"
123 ISR (TIMER1_COMPA_vect) {
124  DEBUGFLOW('/');
125  TIMSK &= ~((1<<TICIE1)|(1<<OCIE1A)|(1<<OCIE1B)|(1<<TOIE1));
126 
127  rtimer_run_next();
128  DEBUGFLOW('\\');
129 }
130 
131 #endif
132 /*---------------------------------------------------------------------------*/
133 void
134 rtimer_arch_init(void)
135 {
136 #if RTIMER_ARCH_PRESCALER
137  /* Disable interrupts (store old state) */
138  uint8_t sreg;
139  sreg = SREG;
140  cli ();
141 
142 #if defined(__AVR_ATxmega256A3__) || defined(__AVR_ATxmega256A3U__)
143  xmega_rtc_rcosc_enable();
144 
145  xmega_rtc_wait_sync_busy();
146 
147  xmega_rtc_set_per(31);
148  xmega_rtc_set_comp(31);
149  xmega_rtc_set_cnt(0);
150 
151  // DIV256
152  xmega_rtc_set_prescaler(RTC_PRESCALER_DIV1_gc);
153 
154  // Use both interrupts here. Overflow interrupt will be used directly for rtimer - compare interrupt is used for contiki timer
155  xmega_rtc_set_interrupt_levels(RTC_OVFINTLVL_LO_gc, RTC_COMPINTLVL_LO_gc);
156 
157  xmega_rtc_wait_sync_busy();
158 #elif defined(__AVR_ATxmega256A3BU__) || defined(__AVR_ATxmega256A3B__)
159  #warning RTC NOT IMPLEMENTED
160 #elif defined(TCNT3)
161 
162  /* Disable all timer functions */
163  ETIMSK &= ~((1 << OCIE3A) | (1 << OCIE3B) | (1 << TOIE3) |
164  (1 << TICIE3) | (1 << OCIE3C));
165  /* Write 1s to clear existing timer function flags */
166  ETIFR |= (1 << ICF3) | (1 << OCF3A) | (1 << OCF3B) | (1 << TOV3) |
167  (1 << OCF3C);
168 
169  /* Default timer behaviour */
170  TCCR3A = 0;
171  TCCR3B = 0;
172  TCCR3C = 0;
173 
174  /* Reset counter */
175  TCNT3 = 0;
176 
177 #if RTIMER_ARCH_PRESCALER==1024
178  TCCR3B |= 5;
179 #elif RTIMER_ARCH_PRESCALER==256
180  TCCR3B |= 4;
181 #elif RTIMER_ARCH_PRESCALER==64
182  TCCR3B |= 3;
183 #elif RTIMER_ARCH_PRESCALER==8
184  TCCR3B |= 2;
185 #elif RTIMER_ARCH_PRESCALER==1
186  TCCR3B |= 1;
187 #else
188 #error Timer3 PRESCALER factor not supported.
189 #endif
190 
191 #elif RTIMER_ARCH_PRESCALER
192  /* Leave timer1 alone if PRESCALER set to zero */
193  /* Obviously you can not then use rtimers */
194 
195  TIMSK &= ~((1<<TICIE1)|(1<<OCIE1A)|(1<<OCIE1B)|(1<<TOIE1));
196  TIFR |= (1 << ICF1) | (1 << OCF1A) | (1 << OCF1B) | (1 << TOV1);
197 
198  /* Default timer behaviour */
199  TCCR1A = 0;
200  TCCR1B = 0;
201 
202  /* Reset counter */
203  TCNT1 = 0;
204 
205  /* Start clock */
206 #if RTIMER_ARCH_PRESCALER==1024
207  TCCR1B |= 5;
208 #elif RTIMER_ARCH_PRESCALER==256
209  TCCR1B |= 4;
210 #elif RTIMER_ARCH_PRESCALER==64
211  TCCR1B |= 3;
212 #elif RTIMER_ARCH_PRESCALER==8
213  TCCR1B |= 2;
214 #elif RTIMER_ARCH_PRESCALER==1
215  TCCR1B |= 1;
216 #else
217  #error Timer1 PRESCALER factor not supported.
218 #endif
219 
220 #endif /* TCNT3 */
221 
222  /* Restore interrupt state */
223  SREG = sreg;
224 #endif /* RTIMER_ARCH_PRESCALER */
225 }
226 /*---------------------------------------------------------------------------*/
227 void
228 rtimer_arch_schedule(rtimer_clock_t t)
229 {
230 #if RTIMER_ARCH_PRESCALER
231  /* Disable interrupts (store old state) */
232  uint8_t sreg;
233  sreg = SREG;
234  cli ();
235  DEBUGFLOW(':');
236 #if defined(__AVR_ATxmega256A3__) || defined(__AVR_ATxmega256A3U__)
237  // uint16_t CNT_pre=RTC_CNT;
238  //stop rtc clearing RTC
239  RTC.CTRL = 0x00;
240  while (RTC.STATUS & RTC_SYNCBUSY_bm) {;}
241 
242  //Set period and trigger overflow interrupt (medium level)
243  RTC.PER = (uint16_t) t;
244  RTC.INTCTRL |= RTC_OVFINTLVL_MED_gc;
245  //start RTC again
246  RTC.CTRL = RTC_PRESCALER_DIV1_gc;
247 
248 #elif defined(__AVR_ATxmega256A3BU__) || defined(__AVR_ATxmega256A3B__)
249  RTC32.CTRL = 0x00;
250 
251  while(RTC32.SYNCCTRL & RTC32_SYNCBUSY_bm);
252 
253  RTC32.PER = (uint16_t) t;
254  RTC32.INTCTRL |= RTC32_OVFINTLVL_LO_gc;
255 
256  RTC32.CTRL |= RTC32_ENABLE_bm;
257 #elif defined(TCNT3)
258  /* Set compare register */
259  OCR3A = t;
260  /* Write 1s to clear all timer function flags */
261  ETIFR |= (1 << ICF3) | (1 << OCF3A) | (1 << OCF3B) | (1 << TOV3) |
262  (1 << OCF3C);
263  /* Enable interrupt on OCR3A match */
264  ETIMSK |= (1 << OCIE3A);
265 
266 #elif RTIMER_ARCH_PRESCALER
267  /* Set compare register */
268  OCR1A = t;
269  TIFR |= (1 << ICF1) | (1 << OCF1A) | (1 << OCF1B) | (1 << TOV1);
270  TIMSK |= (1 << OCIE1A);
271 
272 #endif
273 
274  /* Restore interrupt state */
275  SREG = sreg;
276 #endif /* RTIMER_ARCH_PRESCALER */
277 }
278 
279 #if RDC_CONF_MCU_SLEEP
280 /*---------------------------------------------------------------------------*/
281 void
282 rtimer_arch_sleep(rtimer_clock_t howlong)
283 {
284 /* Deep Sleep for howlong rtimer ticks. This will stop all timers except
285  * for TIMER2 which can be clocked using an external crystal.
286  * Unfortunately this is an 8 bit timer; a lower prescaler gives higher
287  * precision but smaller maximum sleep time.
288  * Here a maximum 128msec (contikimac 8Hz channel check sleep) is assumed.
289  * The rtimer and system clocks are adjusted to reflect the sleep time.
290  */
291 #include <avr/sleep.h>
292 #include <dev/watchdog.h>
293 uint32_t longhowlong;
294 #if AVR_CONF_USE32KCRYSTAL
295 /* Save TIMER2 configuration if clock.c is using it */
296  uint8_t savedTCNT2=TCNT2, savedTCCR2A=TCCR2A, savedTCCR2B = TCCR2B, savedOCR2A = OCR2A;
297 #endif
298  cli();
299  watchdog_stop();
300  set_sleep_mode(SLEEP_MODE_PWR_SAVE);
301 
302 /* Set TIMER2 clock asynchronus from external source, CTC mode */
303  ASSR |= (1 << AS2);
304  TCCR2A =(1<<WGM21);
305 /* Set prescaler and TIMER2 output compare register */
306 #if 0 //Prescale by 1024 - 32 ticks/sec, 8 seconds max sleep
307  TCCR2B =((1<<CS22)|(1<<CS21)|(1<<CS20));
308  longhowlong=howlong*32UL;
309 #elif 0 // Prescale by 256 - 128 ticks/sec, 2 seconds max sleep
310  TCCR2B =((1<<CS22)|(1<<CS21)|(0<<CS20));
311  longhowlong=howlong*128UL;
312 #elif 0 // Prescale by 128 - 256 ticks/sec, 1 seconds max sleep
313  TCCR2B =((1<<CS22)|(0<<CS21)|(1<<CS20));
314  longhowlong=howlong*256UL;
315 #elif 0 // Prescale by 64 - 512 ticks/sec, 500 msec max sleep
316  TCCR2B =((1<<CS22)|(0<<CS21)|(0<<CS20));
317  longhowlong=howlong*512UL;
318 #elif 1 // Prescale by 32 - 1024 ticks/sec, 250 msec max sleep
319  TCCR2B =((0<<CS22)|(1<<CS21)|(1<<CS20));
320  longhowlong=howlong*1024UL;
321 #elif 0 // Prescale by 8 - 4096 ticks/sec, 62.5 msec max sleep
322  TCCR2B =((0<<CS22)|(1<<CS21)|(0<<CS20));
323  longhowlong=howlong*4096UL;
324 #else // No Prescale - 32768 ticks/sec, 7.8 msec max sleep
325  TCCR2B =((0<<CS22)|(0<<CS21)|(1<<CS20));
326  longhowlong=howlong*32768UL;
327 #endif
328  OCR2A = longhowlong/RTIMER_ARCH_SECOND;
329 
330 /* Reset timer count, wait for the write (which assures TCCR2x and OCR2A are finished) */
331  TCNT2 = 0;
332  while(ASSR & (1 << TCN2UB));
333 
334 /* Enable TIMER2 output compare interrupt, sleep mode and sleep */
335  TIMSK2 |= (1 << OCIE2A);
336  SMCR |= (1 << SE);
337  sei();
338  ENERGEST_OFF(ENERGEST_TYPE_CPU);
339  if (OCR2A) sleep_mode();
340  //...zzZZZzz...Ding!//
341 
342 /* Disable sleep mode after wakeup, so random code cant trigger sleep */
343  SMCR &= ~(1 << SE);
344 
345 /* Adjust rtimer ticks if rtimer is enabled. TIMER3 is preferred, else TIMER1 */
346 #if RTIMER_ARCH_PRESCALER
347 #ifdef TCNT3
348  TCNT3 += howlong;
349 #else
350  TCNT1 += howlong;
351 #endif
352 #endif
353  ENERGEST_ON(ENERGEST_TYPE_CPU);
354 
355 #if AVR_CONF_USE32KCRYSTAL
356 /* Restore clock.c configuration */
357  cli();
358  TCCR2A = savedTCCR2A;
359  TCCR2B = savedTCCR2B;
360  OCR2A = savedOCR2A;
361  TCNT2 = savedTCNT2;
362  sei();
363 #else
364 /* Disable TIMER2 interrupt */
365  TIMSK2 &= ~(1 << OCIE2A);
366 #endif
367  watchdog_start();
368 
369 /* Adjust clock.c for the time spent sleeping */
370  longhowlong=CLOCK_CONF_SECOND;
371  longhowlong*=howlong;
372  clock_adjust_ticks(longhowlong/RTIMER_ARCH_SECOND);
373 
374 }
375 #if !AVR_CONF_USE32KCRYSTAL
376 /*---------------------------------------------------------------------------*/
377 /* TIMER2 Interrupt service */
378 
379 ISR(TIMER2_COMPA_vect)
380 {
381 // TIMSK2 &= ~(1 << OCIE2A); //Just one interrupt needed for waking
382 }
383 #endif /* !AVR_CONF_USE32KCRYSTAL */
384 #endif /* RDC_CONF_MCU_SLEEP */
385 
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