Contiki-Inga 3.x
ssi.h
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1 /*
2  * Copyright (c) 2013, University of Michigan.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  * notice, this list of conditions and the following disclaimer in the
12  * documentation and/or other materials provided with the distribution.
13  * 3. Neither the name of the University nor the names of its contributors
14  * may be used to endorse or promote products derived from this software
15  * without specific prior written permission.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE INSTITUTE AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED. IN NO EVENT SHALL THE INSTITUTE OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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28  */
29 /**
30  * \addtogroup cc2538
31  * @{
32  *
33  * \defgroup cc2538-spi cc2538 Synchronous Serial Interface
34  *
35  * Driver for the cc2538 SPI peripheral
36  *
37  * Register and bitmask definitions based on the Foundation Firmware from
38  * Texas Instruments.
39  * @{
40  *
41  * \file
42  * Header file for the cc2538 Synchronous Serial Interface
43  */
44 
45 #ifndef SSI_H_
46 #define SSI_H_
47 
48 /*---------------------------------------------------------------------------*/
49 /** \name Base register memory locations.
50  * @{
51  */
52 #define SSI0_BASE 0x40008000 /**< Base address for SSI0 */
53 #define SSI1_BASE 0x40009000 /**< Base address for SSI1 */
54 /** @} */
55 /*---------------------------------------------------------------------------*/
56 /** \name SSI register offsets
57  * @{
58  */
59 #define SSI_CR0 0x00000000 /**< Control register 0 */
60 #define SSI_CR1 0x00000004 /**< Control register 1 */
61 #define SSI_DR 0x00000008 /**< Access the TX and RX FIFO */
62 #define SSI_SR 0x0000000C /**< Meta information about FIFO */
63 #define SSI_CPSR 0x00000010 /**< Clock divider */
64 #define SSI_IM 0x00000014 /**< Interrupt mask */
65 #define SSI_RIS 0x00000018 /**< Raw interrupt status */
66 #define SSI_MIS 0x0000001C /**< Masked interrupt status */
67 #define SSI_ICR 0x00000020 /**< Interrupt clear register */
68 #define SSI_DMACTL 0x00000024 /**< DMA control register */
69 #define SSI_CC 0x00000FC8 /**< Clock configuration */
70 /** @} */
71 /*---------------------------------------------------------------------------*/
72 /** \name SSI Bitmasks and shifts
73  * @{
74  */
75 #define SSI_CR0_SCR_M 0x0000FF00 /**< Serial clock rate mask */
76 #define SSI_CR0_SCR_S 8 /**< Serial clock rate shift */
77 #define SSI_CR0_SPH 0x00000080 /**< Serial clock phase (H) */
78 #define SSI_CR0_SPH_M 0x00000080 /**< Serial clock phase (H) mask */
79 #define SSI_CR0_SPH_S 7 /**< Serial clock phase (H) shift */
80 #define SSI_CR0_SPO 0x00000040 /**< Serial clock phase (O) */
81 #define SSI_CR0_SPO_M 0x00000040 /**< Serial clock phase (O) mask */
82 #define SSI_CR0_SPO_S 6 /**< Serial clock phase (O) shift */
83 #define SSI_CR0_FRF_M 0x00000030 /**< Frame format select mask */
84 #define SSI_CR0_FRF_S 4 /**< Frame format select shift */
85 #define SSI_CR0_DSS_M 0x0000000F /**< Data size select mask */
86 #define SSI_CR0_DSS_S 0 /**< Data size select shift */
87 #define SSI_CR1_SOD 0x00000008 /**< Slave mode output disable */
88 #define SSI_CR1_SOD_M 0x00000008 /**< Slave mode output disable mask */
89 #define SSI_CR1_SOD_S 3 /**< Slave mode output disable shift */
90 #define SSI_CR1_MS 0x00000004 /**< Master and slave select */
91 #define SSI_CR1_MS_M 0x00000004 /**< Master and slave select mask */
92 #define SSI_CR1_MS_S 2 /**< Master and slave select shift */
93 #define SSI_CR1_SSE 0x00000002 /**< Synchronous serial port enable */
94 #define SSI_CR1_SSE_M 0x00000002 /**< Synchronous serial port enable mask */
95 #define SSI_CR1_SSE_S 1 /**< Synchronous serial port enable shift */
96 #define SSI_CR1_LBM 0x00000001 /**< Loop-back mode */
97 #define SSI_CR1_LBM_M 0x00000001 /**< Loop-back mode mask */
98 #define SSI_CR1_LBM_S 0 /**< Loop-back mode shift */
99 #define SSI_DR_DATA_M 0x0000FFFF /**< FIFO data mask */
100 #define SSI_DR_DATA_S 0 /**< FIFO data shift */
101 #define SSI_SR_BSY 0x00000010 /**< Busy bit */
102 #define SSI_SR_BSY_M 0x00000010 /**< Busy bit mask */
103 #define SSI_SR_BSY_S 4 /**< Busy bit shift */
104 #define SSI_SR_RFF 0x00000008 /**< Receive FIFO full */
105 #define SSI_SR_RFF_M 0x00000008 /**< Receive FIFO full mask */
106 #define SSI_SR_RFF_S 3 /**< Receive FIFO full shift */
107 #define SSI_SR_RNE 0x00000004 /**< Receive FIFO not empty */
108 #define SSI_SR_RNE_M 0x00000004 /**< Receive FIFO not empty mask */
109 #define SSI_SR_RNE_S 2 /**< Receive FIFO not empty shift */
110 #define SSI_SR_TNF 0x00000002 /**< Transmit FIFO not full */
111 #define SSI_SR_TNF_M 0x00000002 /**< Transmit FIFO not full mask */
112 #define SSI_SR_TNF_S 1 /**< Transmit FIFO not full shift */
113 #define SSI_SR_TFE 0x00000001 /**< Transmit FIFO empty */
114 #define SSI_SR_TFE_M 0x00000001 /**< Transmit FIFO empty mask */
115 #define SSI_SR_TFE_S 0 /**< Transmit FIFO empty shift */
116 #define SSI_CPSR_CPSDVSR_M 0x000000FF /**< Clock prescale divisor mask */
117 #define SSI_CPSR_CPSDVSR_S 0 /**< Clock prescale divisor shift */
118 #define SSI_IM_TXIM 0x00000008 /**< Transmit FIFO interrupt mask */
119 #define SSI_IM_TXIM_M 0x00000008 /**< Transmit FIFO interrupt mask mask */
120 #define SSI_IM_TXIM_S 3 /**< Transmit FIFO interrupt mask shift */
121 #define SSI_IM_RXIM 0x00000004 /**< Receive FIFO interrupt mask */
122 #define SSI_IM_RXIM_M 0x00000004 /**< Receive FIFO interrupt mask mask */
123 #define SSI_IM_RXIM_S 2 /**< Receive FIFO interrupt mask shift */
124 #define SSI_IM_RTIM 0x00000002 /**< Receive time-out interrupt mask */
125 #define SSI_IM_RTIM_M 0x00000002 /**< Receive time-out interrupt mask mask */
126 #define SSI_IM_RTIM_S 1 /**< Receive time-out interrupt mask shift */
127 #define SSI_IM_RORIM 0x00000001 /**< Receive overrun interrupt mask */
128 #define SSI_IM_RORIM_M 0x00000001 /**< Receive overrun interrupt mask mask */
129 #define SSI_IM_RORIM_S 0 /**< Receive overrun interrupt mask shift */
130 #define SSI_RIS_TXRIS 0x00000008 /**< SSITXINTR raw state */
131 #define SSI_RIS_TXRIS_M 0x00000008 /**< SSITXINTR raw state mask */
132 #define SSI_RIS_TXRIS_S 3 /**< SSITXINTR raw state shift */
133 #define SSI_RIS_RXRIS 0x00000004 /**< SSIRXINTR raw state */
134 #define SSI_RIS_RXRIS_M 0x00000004 /**< SSIRXINTR raw state mask */
135 #define SSI_RIS_RXRIS_S 2 /**< SSIRXINTR raw state shift */
136 #define SSI_RIS_RTRIS 0x00000002 /**< SSIRTINTR raw state */
137 #define SSI_RIS_RTRIS_M 0x00000002 /**< SSIRTINTR raw state mask */
138 #define SSI_RIS_RTRIS_S 1 /**< SSIRTINTR raw state shift */
139 #define SSI_RIS_RORRIS 0x00000001 /**< SSIRORINTR raw state */
140 #define SSI_RIS_RORRIS_M 0x00000001 /**< SSIRORINTR raw state mask */
141 #define SSI_RIS_RORRIS_S 0 /**< SSIRORINTR raw state shift */
142 #define SSI_MIS_TXMIS 0x00000008 /**< SSITXINTR masked state */
143 #define SSI_MIS_TXMIS_M 0x00000008 /**< SSITXINTR masked state mask */
144 #define SSI_MIS_TXMIS_S 3 /**< SSITXINTR masked state shift */
145 #define SSI_MIS_RXMIS 0x00000004 /**< SSIRXINTR masked state */
146 #define SSI_MIS_RXMIS_M 0x00000004 /**< SSIRXINTR masked state mask */
147 #define SSI_MIS_RXMIS_S 2 /**< SSIRXINTR masked state shift */
148 #define SSI_MIS_RTMIS 0x00000002 /**< SSIRTINTR masked state */
149 #define SSI_MIS_RTMIS_M 0x00000002 /**< SSIRTINTR masked state mask */
150 #define SSI_MIS_RTMIS_S 1 /**< SSIRTINTR masked state shift */
151 #define SSI_MIS_RORMIS 0x00000001 /**< SSIRORINTR masked state */
152 #define SSI_MIS_RORMIS_M 0x00000001 /**< SSIRORINTR masked state mask */
153 #define SSI_MIS_RORMIS_S 0 /**< SSIRORINTR masked state shift */
154 #define SSI_ICR_RTIC 0x00000002 /**< Receive time-out interrupt clear */
155 #define SSI_ICR_RTIC_M 0x00000002 /**< Receive time-out interrupt clear mask */
156 #define SSI_ICR_RTIC_S 1 /**< Receive time-out interrupt clear shift */
157 #define SSI_ICR_RORIC 0x00000001 /**< Receive overrun interrupt clear */
158 #define SSI_ICR_RORIC_M 0x00000001 /**< Receive overrun interrupt clear mask */
159 #define SSI_ICR_RORIC_S 0 /**< Receive overrun interrupt clear shift */
160 #define SSI_DMACTL_TXDMAE 0x00000002 /**< Transmit DMA enable */
161 #define SSI_DMACTL_TXDMAE_M 0x00000002 /**< Transmit DMA enable mask */
162 #define SSI_DMACTL_TXDMAE_S 1 /**< Transmit DMA enable shift */
163 #define SSI_DMACTL_RXDMAE 0x00000001 /**< Receive DMA enable */
164 #define SSI_DMACTL_RXDMAE_M 0x00000001 /**< Receive DMA enable mask */
165 #define SSI_DMACTL_RXDMAE_S 0 /**< Receive DMA enable shift */
166 #define SSI_CC_CS_M 0x00000007 /**< Baud and system clock source mask */
167 #define SSI_CC_CS_S 0 /**< Baud and system clock source shift */
168 /** @} */
169 
170 #endif
171 /**
172  * @}
173  * @}
174  */
175 
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