Contiki-Inga 3.x
cc2430_sfr.h
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1 /**
2  *
3  * \file cc2430_sfr.h
4  * \brief CC2430 registers header file for CC2430.
5  *
6  * Definitions for CC2430 SFR registers.
7  *
8  *
9  */
10 
11 #ifndef REG_CC2430_H
12 #define REG_CC2430_H
13 
14 #include "8051def.h"
15 
16 /* BYTE Register */
17 
18 __sfr __at (0x80) P0 ;
19 /* P0 */
20 __sbit __at (0x87) P0_7 ;
21 __sbit __at (0x86) P0_6 ;
22 __sbit __at (0x85) P0_5 ;
23 __sbit __at (0x84) P0_4 ;
24 __sbit __at (0x83) P0_3 ;
25 __sbit __at (0x82) P0_2 ;
26 __sbit __at (0x81) P0_1 ;
27 __sbit __at (0x80) P0_0 ;
28 
29 __sfr __at (0x81) SP ;
30 __sfr __at (0x82) DPL0 ;
31 __sfr __at (0x83) DPH0 ;
32 /*DPL and DPH correspond DPL0 and DPH0 (82-83)*/
33 __sfr __at (0x84) DPL1;
34 __sfr __at (0x85) DPH1;
35 __sfr __at (0x86) U0CSR;
36 #define U_MODE 0x80
37 #define U_RE 0x40
38 #define U_SLAVE 0x20
39 #define U_FE 0x10
40 #define U_ERR 0x08
41 #define U_RXB 0x04
42 #define U_TXB 0x02
43 #define U_ACTIVE 0x01
44 
45 __sfr __at (0x87) PCON ;
46 /* PCON (0x87) */
47 #define IDLE 0x01
48 
49 __sfr __at (0x88) TCON ;
50 /* TCON (0x88) */
51 __sbit __at (0x8F) TCON_URX1IF;
52 /*__sbit __at (0x8E) RES;*/
53 __sbit __at (0x8D) TCON_ADCIF;
54 /*__sbit __at (0x8C) RES;*/
55 __sbit __at (0x8B) TCON_URX0IF;
56 __sbit __at (0x8A) TCON_IT1;
57 __sbit __at (0x89) TCON_RFERRIF;
58 __sbit __at (0x88) TCON_IT0;
59 
60 
61 __sfr __at (0x89) P0IFG;
62 __sfr __at (0x8A) P1IFG;
63 __sfr __at (0x8B) P2IFG;
64 __sfr __at (0x8C) PICTL;
65 /*PICTL bits*/
66 #define PADSC 0x40
67 #define P2IEN 0x20
68 #define P0IENH 0x10
69 #define P0IENL 0x08
70 #define P2ICON 0x04
71 #define P1ICON 0x02
72 #define P0ICON 0x01
73 
74 __sfr __at (0x8D) P1IEN;
75 __sfr __at (0x8F) P0INP;
76 
77 __sfr __at (0x90) P1 ;
78 /* P1 */
79 __sbit __at (0x90) P1_0 ;
80 __sbit __at (0x91) P1_1 ;
81 __sbit __at (0x92) P1_2 ;
82 __sbit __at (0x93) P1_3 ;
83 __sbit __at (0x94) P1_4 ;
84 __sbit __at (0x95) P1_5 ;
85 __sbit __at (0x96) P1_6 ;
86 __sbit __at (0x97) P1_7 ;
87 
88 __sfr __at (0x91) RFIM;
89 __sfr __at (0x92) DPS;
90 __sfr __at (0x93) _XPAGE; /*MPAGE as paging register for sdcc*/
91 __sfr __at (0x94) T2CMP;
92 __sfr __at (0x95) ST0;
93 __sfr __at (0x96) ST1;
94 __sfr __at (0x97) ST2;
95 __sfr __at (0x98) S0CON ;
96 
97 __sbit __at (0x99) S0CON_ENCIF_1;
98 __sbit __at (0x98) S0CON_ENCIF_0;
99 
100 __sfr __at (0x99) HSRC;
101 __sfr __at (0x9A) IEN2;
102 /*IEN2 bits*/
103 #define WDTIE 0x20
104 #define P1IE 0x10
105 #define UTX1IE 0x08
106 #define UTX0IE 0x04
107 #define P2IE 0x02
108 #define RFIE 0x01
109 __sfr __at (0x9B) S1CON;
110 /*S1CON bits*/
111 #define RFIF_1 0x02
112 #define RFIF_0 0x01
113 __sfr __at (0x9C) T2PEROF0;
114 __sfr __at (0x9D) T2PEROF1;
115 __sfr __at (0x9E) T2PEROF2;
116 /*T2PEROF2 bits*/
117 #define CMPIM 0x80
118 #define PERIM 0x40
119 #define OFCMPIM 0x20
120 
121 #define PEROF23 0x08
122 #define PEROF22 0x04
123 #define PEROF21 0x02
124 #define PEROF20 0x01
125 
126 __sfr __at (0x9F) FMAP;
127 __sfr __at (0x9F) PSBANK;
128 
129 __sfr __at (0xA0) P2 ;
130 /* P2 */
131 __sbit __at (0xA0) P2_0 ;
132 __sbit __at (0xA1) P2_1 ;
133 __sbit __at (0xA2) P2_2 ;
134 __sbit __at (0xA3) P2_3 ;
135 __sbit __at (0xA4) P2_4 ;
136 /*__sbit __at (0xA5) P2_5 ;
137 __sbit __at (0xA6) P2_6 ;
138 __sbit __at (0xA7) P2_7 ;*/
139 
140 __sfr __at (0xA1) T2OF0;
141 __sfr __at (0xA2) T2OF1;
142 __sfr __at (0xA3) T2OF2;
143 __sfr __at (0xA4) T2CAPLPL;
144 __sfr __at (0xA5) T2CAPHPH;
145 __sfr __at (0xA6) T2TLD;
146 __sfr __at (0xA7) T2THD;
147 
148 __sfr __at (0xA8) IE ;
149 __sfr __at (0xA8) IEN0;
150 /*IEN0 bits*/
151 #define IEN0_EA_MASK 0x80
152 #define STIE 0x20
153 #define ENCIE 0x10
154 #define URX1IE 0x08
155 #define URX0IE 0x04
156 #define ADCIE 0x02
157 #define RFERRIE 0x01
158 /* IEN0 (0xA8) */
159 __sbit __at (0xAF) EA;
160 __sbit __at (0xAF) IEN0_EA;
161 /*__sbit __at (0xAE) RES;*/
162 __sbit __at (0xAD) IEN0_STIE;
163 __sbit __at (0xAC) IEN0_ENCIE;
164 __sbit __at (0xAB) IEN0_URX1IE;
165 __sbit __at (0xAA) IEN0_URX0IE;
166 __sbit __at (0xA9) IEN0_ADCIE;
167 __sbit __at (0xA8) IEN0_RFERRIE;
168 
169 __sfr __at (0xA9) IP0;
170 /*IP0 bits*/
171 #define IP0_5 0x20
172 #define IP0_4 0x10
173 #define IP0_3 0x08
174 #define IP0_2 0x04
175 #define IP0_1 0x02
176 #define IP0_0 0x01
177 __sfr __at (0xAB) FWT;
178 __sfr __at (0xAC) FADDRL;
179 __sfr __at (0xAD) FADDRH;
180 
181 __sfr __at (0xAE) FCTL;
182 #define F_BUSY 0x80
183 #define F_SWBSY 0x40
184 #define F_CONTRD 0x10
185 #define F_WRITE 0x02
186 #define F_ERASE 0x01
187 __sfr __at (0xAF) FWDATA;
188 
189 /*No port 3 (0xB0)*/
190 __sfr __at (0xB1) ENCDI;
191 __sfr __at (0xB2) ENCDO;
192 __sfr __at (0xB3) ENCCS;
193 #define CCS_MODE2 0x40
194 #define CCS_MODE1 0x20
195 #define CCS_MODE0 0x10
196 #define CCS_RDY 0x08
197 #define CCS_CMD1 0x04
198 #define CCS_CMD0 0x02
199 #define CCS_ST 0x01
200 __sfr __at (0xB4) ADCCON1;
201 /*ADCCON1 bits*/
202 #define ADEOC 0x80
203 #define ADST 0x40
204 #define ADSTS1 0x20
205 #define ADSTS0 0x10
206 #define ADRCTRL1 0x08
207 #define ADRCTRL0 0x04
208 __sfr __at (0xB5) ADCCON2;
209 /*ADCCON2 bits*/
210 #define ADSREF1 0x80
211 #define ADSREF0 0x40
212 #define ADSDIV1 0x20
213 #define ADSDIV0 0x10
214 #define ADSCH3 0x08
215 #define ADSCH2 0x04
216 #define ADSCH1 0x02
217 #define ADSCH0 0x01
218 __sfr __at (0xB6) ADCCON3;
219 /*ADCCON3 bits*/
220 #define ADEREF1 0x80
221 #define ADEREF0 0x40
222 #define ADEDIV1 0x20
223 #define ADEDIV0 0x10
224 #define ADECH3 0x08
225 #define ADECH2 0x04
226 #define ADECH1 0x02
227 #define ADECH0 0x01
228 
229 __sfr __at (0xB7) RCCTL;
230 #undef IP /*this is 0xb8 in base core*/
231 
232 __sfr __at (0xB8) IEN1;
233 /*IEN1 bits*/
234 #define P0IE 0x20
235 #define T4IE 0x10
236 #define T3IE 0x08
237 #define T2IE 0x04
238 #define T1IE 0x02
239 #define DMAIE 0x01
240 /* IEN1 (0xB8) */
241 /*__sbit __at (0xBF) IEN1_RES;*/
242 /*__sbit __at (0xBE) RES;*/
243 __sbit __at (0xBD) IEN1_P0IE;
244 __sbit __at (0xBC) IEN1_T4IE;
245 __sbit __at (0xBB) IEN1_T3IE;
246 __sbit __at (0xBA) IEN1_T2IE;
247 __sbit __at (0xB9) IEN1_T1IE;
248 __sbit __at (0xB8) IEN1_DMAIE;
249 
250 __sfr __at (0xB9) IP1;
251 /*IP1 bits*/
252 #define IP1_5 0x20
253 #define IP1_4 0x10
254 #define IP1_3 0x08
255 #define IP1_2 0x04
256 #define IP1_1 0x02
257 #define IP1_0 0x01
258 
259 __sfr __at (0xBA) ADCL;
260 __sfr __at (0xBB) ADCH;
261 __sfr __at (0xBC) RNDL;
262 __sfr __at (0xBD) RNDH;
263 
264 __sfr __at (0xBE) SLEEP;
265 #define OSC32K_CALDIS 0x80
266 #define XOSC_STB 0x40
267 #define HFRC_STB 0x20
268 #define RST1 0x10
269 #define RST0 0x08
270 #define OSC_PD 0x04
271 #define SLEEP_MODE1 0x02
272 #define SLEEP_MODE0 0x01
273 
274 __sfr __at (0xC0) IRCON;
275 /*IRCON bits*/
276 #define STIF 0x80
277 #define P0IF 0x20
278 #define T4IF 0x10
279 #define T3IF 0x08
280 #define T2IF 0x04
281 #define T1IF 0x02
282 #define DMAIF 0x01
283 /* IRCON */
284 __sbit __at (0xC7) IRCON_STIF ;
285 /*__sbit __at (0x86) IRCON_6 ;*/
286 __sbit __at (0xC5) IRCON_P0IF;
287 __sbit __at (0xC4) IRCON_T4IF;
288 __sbit __at (0xC3) IRCON_T3IF;
289 __sbit __at (0xC2) IRCON_T2IF;
290 __sbit __at (0xC1) IRCON_T1IF;
291 __sbit __at (0xC0) IRCON_DMAIF;
292 
293 __sfr __at (0xC1) U0BUF;
294 
295 __sfr __at (0xC2) U0BAUD;
296 __sfr __at (0xC3) T2CNF;
297 /*T2SEL bits*/
298 #define CMPIF 0x80
299 #define PERIF 0x40
300 #define OFCMPIF 0x20
301 
302 #define CMSEL 0x08
303 
304 #define SYNC 0x02
305 #define RUN 0x01
306 
307 __sfr __at (0xC4) U0UCR;
308 #define U_FLUSH 0x80
309 #define U_FLOW 0x40
310 #define U_D9 0x20
311 #define U_BIT9 0x10
312 #define U_PARITY 0x08
313 #define U_SPB 0x04
314 #define U_STOP 0x02
315 #define U_START 0x01
316 
317 __sfr __at (0xC5) U0GCR;
318 #define U_CPOL 0x80
319 #define U_CPHA 0x40
320 #define U_ORDER 0x20
321 #define U_BAUD_E4 0x10
322 #define U_BAUD_E3 0x08
323 #define U_BAUD_E2 0x04
324 #define U_BAUD_E1 0x02
325 #define U_BAUD_E0 0x01
326 
327 __sfr __at (0xC6) CLKCON;
328 #define OSC32K 0x80
329 #define OSC 0x40
330 #define TICKSPD2 0x20
331 #define TICKSPD1 0x10
332 #define TICKSPD0 0x08
333 #define CLKSPD 0x01
334 
335 __sfr __at (0xC7) MEMCTR;
336 #define MUNIF 0x40
337 __sfr __at (0xC8) T2CON;
338 
339 __sfr __at (0xC9) WDCTL;
340 #define WDT_CLR3 0x80
341 #define WDT_CLR2 0x40
342 #define WDT_CLR1 0x20
343 #define WDT_CLR0 0x10
344 #define WDT_EN 0x08
345 #define WDT_MODE 0x04
346 #define WDT_INT1 0x02
347 #define WDT_INT0 0x01
348 
349 __sfr __at (0xCA) T3CNT;
350 
351 __sfr __at (0xCB) T3CTL;
352 /*T3CTL bits*/
353 #define T3DIV2 0x80
354 #define T3DIV1 0x40
355 #define T3DIV0 0x20
356 #define T3START 0x10
357 #define T3OVFIM 0x08
358 #define T3CLR 0x04
359 #define T3MODE1 0x02
360 #define T3MODE0 0x01
361 
362 __sfr __at (0xCC) T3CCTL0;
363 /*T3CCTL0 bits*/
364 #define T3IM 0x40
365 #define T3CMP2 0x20
366 #define T3CMP1 0x10
367 #define T3CMP0 0x08
368 #define T3MODE 0x04
369 #define T3CAP1 0x02
370 #define T3CAP0 0x01
371 
372 __sfr __at (0xCD) T3CC0;
373 __sfr __at (0xCE) T3CCTL1;
374 /*T3CCTL0 bits apply*/
375 __sfr __at (0xCF) T3CC1;
376 
377 __sfr __at (0xD0) PSW ;
378 /* PSW */
379 __sbit __at (0xD0) P ;
380 __sbit __at (0xD1) F1 ;
381 __sbit __at (0xD2) OV ;
382 __sbit __at (0xD3) RS0 ;
383 __sbit __at (0xD4) RS1 ;
384 __sbit __at (0xD5) F0 ;
385 __sbit __at (0xD6) AC ;
386 __sbit __at (0xD7) CY ;
387 
388 __sfr __at (0xD1) DMAIRQ;
389 /*DMAIRQ bits*/
390 #define DMAIF4 0x10
391 #define DMAIF3 0x08
392 #define DMAIF2 0x04
393 #define DMAIF1 0x02
394 #define DMAIF0 0x01
395 
396 __sfr __at (0xD2) DMA1CFGL;
397 __sfr __at (0xD3) DMA1CFGH;
398 __sfr __at (0xD4) DMA0CFGL;
399 __sfr __at (0xD5) DMA0CFGH;
400 
401 __sfr __at (0xD6) DMAARM;
402 /*DMAARM bits*/
403 #define ABORT 0x80
404 #define DMAARM4 0x10
405 #define DMAARM3 0x08
406 #define DMAARM2 0x04
407 #define DMAARM1 0x02
408 #define DMAARM0 0x01
409 
410 __sfr __at (0xD7) DMAREQ;
411 /*DMAREQ bits*/
412 #define DMAREQ4 0x10
413 #define DMAREQ3 0x08
414 #define DMAREQ2 0x04
415 #define DMAREQ1 0x02
416 #define DMAREQ0 0x01
417 
418 __sfr __at (0xD8) TIMIF;
419 /*TIMIF bits*/
420 #define OVFIM 0x40
421 #define T4CH1IF 0x20
422 #define T4CH0IF 0x10
423 #define T4OVFIF 0x08
424 #define T3CH1IF 0x04
425 #define T3CH0IF 0x02
426 #define T3OVFIF 0x01
427 
428 __sfr __at (0xD9) RFD;
429 __sfr __at (0xDA) T1CC0L;
430 __sfr __at (0xDB) T1CC0H;
431 __sfr __at (0xDC) T1CC1L;
432 __sfr __at (0xDD) T1CC1H;
433 __sfr __at (0xDE) T1CC2L;
434 __sfr __at (0xDF) T1CC2H;
435 
436 __sfr __at (0xE0) ACC;
437 __sfr __at (0xE1) RFST;
438 __sfr __at (0xE2) T1CNTL;
439 __sfr __at (0xE3) T1CNTH;
440 
441 __sfr __at (0xE4) T1CTL;
442 /*T1CTL bits*/
443 #define CH2IF 0x80
444 #define CH1IF 0x40
445 #define CH0IF 0x20
446 #define OVFIF 0x10
447 #define T1DIV1 0x08
448 #define T1DIV0 0x04
449 #define T1MODE1 0x02
450 #define T1MODE0 0x01
451 
452 __sfr __at (0xE5) T1CCTL0;
453 /*T1CCTL0 bits*/
454 #define T1CPSEL 0x80
455 #define T1IM 0x40
456 #define T1CMP2 0x20
457 #define T1CMP1 0x10
458 #define T1CMP0 0x08
459 #define T1MODE 0x04
460 #define T1CAP1 0x02
461 #define T1CAP0 0x01
462 
463 __sfr __at (0xE6) T1CCTL1;
464 /*Bits defined in T1CCTL0 */
465 __sfr __at (0xE7) T1CCTL2;
466 /*Bits defined in T1CCTL0 */
467 __sfr __at (0xE8) IRCON2;
468 /*IRCON2 bits*/
469 #define WDTIF 0x10
470 #define P1IF 0x08
471 #define UTX1IF 0x04
472 #define UTX0IF 0x02
473 #define P2IF 0x01
474 /* IRCON 2 */
475 /*__sbit __at (0xEF) IRCON2_P1_7 ;
476 __sbit __at (0xEE) IRCON2_P1_6 ;
477 __sbit __at (0xED) IRCON2_P1_5 ;*/
478 __sbit __at (0xEC) IRCON2_WDTIF ;
479 __sbit __at (0xEB) IRCON2_P1IF ;
480 __sbit __at (0xEA) IRCON2_UTX1IF ;
481 __sbit __at (0xE9) IRCON2_UTX0IF ;
482 __sbit __at (0xE8) IRCON2_P2IF;
483 
484 
485 __sfr __at (0xE9) RFIF;
486 /*RFIF bits*/
487 #define IRQ_RREG_ON 0x80
488 #define IRQ_TXDONE 0x40
489 #define IRQ_FIFOP 0x20
490 #define IRQ_SFD 0x10
491 #define IRQ_CCA 0x08
492 #define IRQ_CSP_WT 0x04
493 #define IRQ_CSP_STOP 0x02
494 #define IRQ_CSP_INT 0x01
495 
496 __sfr __at (0xEA) T4CNT;
497 __sfr __at (0xEB) T4CTL;
498 /*T4CTL bits*/
499 #define T4DIV2 0x80
500 #define T4DIV1 0x40
501 #define T4DIV0 0x20
502 #define T4START 0x10
503 #define T4OVFIM 0x08
504 #define T4CLR 0x04
505 #define T4MODE1 0x02
506 #define T4MODE0 0x01
507 
508 __sfr __at (0xEC) T4CCTL0;
509 /*T4CCTL0 bits*/
510 #define T4IM 0x40
511 #define T4CMP2 0x20
512 #define T4CMP1 0x10
513 #define T4CMP0 0x08
514 #define T4MODE 0x04
515 #define T4CAP1 0x02
516 #define T4CAP0 0x01
517 
518 __sfr __at (0xED) T4CC0;
519 __sfr __at (0xEE) T4CCTL1;
520 /*T4CCTL0 bits apply*/
521 __sfr __at (0xEF) T4CC1;
522 
523 __sfr __at (0xF0) B ;
524 __sfr __at (0xF1) PERCFG;
525 /*PERCFG bits*/
526 #define T1CFG 0x40
527 #define T3CFG 0x20
528 #define T4CFG 0x10
529 #define U1CFG 0x02
530 #define U0CFG 0x01
531 
532 __sfr __at (0xF2) ADCCFG;
533 /*ADCCFG bits*/
534 #define ADC7EN 0x80
535 #define ADC6EN 0x40
536 #define ADC5EN 0x20
537 #define ADC4EN 0x10
538 #define ADC3EN 0x08
539 #define ADC2EN 0x04
540 #define ADC1EN 0x02
541 #define ADC0EN 0x01
542 
543 __sfr __at (0xF3) P0SEL;
544 __sfr __at (0xF4) P1SEL;
545 __sfr __at (0xF5) P2SEL;
546 /*P2SEL bits*/
547 #define PRI3P1 0x40
548 #define PRI2P1 0x20
549 #define PRI1P1 0x10
550 #define PRI0P1 0x08
551 #define SELP2_4 0x04
552 #define SELP2_3 0x02
553 #define SELP2_0 0x01
554 
555 __sfr __at (0xF6) P1INP;
556 
557 __sfr __at (0xF7) P2INP;
558 /*P2INP bits*/
559 #define PDUP2 0x80
560 #define PDUP1 0x40
561 #define PDUP0 0x20
562 #define MDP2_4 0x10
563 #define MDP2_3 0x08
564 #define MDP2_2 0x04
565 #define MDP2_1 0x02
566 #define MDP2_0 0x01
567 
568 __sfr __at (0xF8) U1CSR;
569 __sfr __at (0xF9) U1BUF;
570 __sfr __at (0xFA) U1BAUD;
571 __sfr __at (0xFB) U1UCR;
572 __sfr __at (0xFC) U1GCR;
573 __sfr __at (0xFD) P0DIR;
574 __sfr __at (0xFE) P1DIR;
575 
576 __sfr __at (0xFF) P2DIR;
577 /*P2DIR bits*/
578 #define PRI1P0 0x80
579 #define PRI0P0 0x40
580 #define DIRP2_4 0x10
581 #define DIRP2_3 0x08
582 #define DIRP2_2 0x04
583 #define DIRP2_1 0x02
584 #define DIRP2_0 0x01
585 
586 /* IEN0 */
587 /*__sbit __at (0xA8) EA ;
588 __sbit __at (0x99) TI ;
589 __sbit __at (0x9A) RB8 ;
590 __sbit __at (0x9B) TB8 ;
591 __sbit __at (0x9C) REN ;
592 __sbit __at (0x9D) SM2 ;
593 __sbit __at (0x9E) SM1 ;
594 __sbit __at (0x9F) SM0 ;*/
595 
596 
597 
598 /* Interrupt numbers: address = (number * 8) + 3 */
599 /*#undef IE0_VECTOR
600 #undef TF0_VECTOR
601 #undef IE1_VECTOR
602 #undef TF1_VECTOR
603 #undef SI0_VECTOR*/
604 
605 /* CC2430 interrupt vectors */
606 #define RFERR_VECTOR 0
607 #define ADC_VECTOR 1
608 #define URX0_VECTOR 2
609 #define URX1_VECTOR 3
610 #define ENC_VECTOR 4
611 #define ST_VECTOR 5
612 #define P2INT_VECTOR 6
613 #define UTX0_VECTOR 7
614 #define DMA_VECTOR 8
615 #define T1_VECTOR 9
616 #define T2_VECTOR 10
617 #define T3_VECTOR 11
618 #define T4_VECTOR 12
619 #define P0INT_VECTOR 13
620 #define UTX1_VECTOR 14
621 #define P1INT_VECTOR 15
622 #define RF_VECTOR 16
623 #define WDT_VECTOR 17
624 
625 /* RF control registers*/
626 __xdata __at (0xDF02) unsigned char MDMCTRL0H;
627 __xdata __at (0xDF03) unsigned char MDMCTRL0L;
628 __xdata __at (0xDF04) unsigned char MDMCTRL1H;
629 __xdata __at (0xDF05) unsigned char MDMCTRL1L;
630 __xdata __at (0xDF06) unsigned char RSSIH;
631 __xdata __at (0xDF07) unsigned char RSSIL;
632 __xdata __at (0xDF08) unsigned char SYNCWORDH;
633 __xdata __at (0xDF09) unsigned char SYNCWORDL;
634 __xdata __at (0xDF0A) unsigned char TXCTRLH;
635 __xdata __at (0xDF0B) unsigned char TXCTRLL;
636 __xdata __at (0xDF0C) unsigned char RXCTRL0H;
637 __xdata __at (0xDF0D) unsigned char RXCTRL0L;
638 __xdata __at (0xDF0E) unsigned char RXCTRL1H;
639 __xdata __at (0xDF0F) unsigned char RXCTRL1L;
640 __xdata __at (0xDF10) unsigned char FSCTRLH;
641 __xdata __at (0xDF11) unsigned char FSCTRLL;
642 __xdata __at (0xDF12) unsigned char CSPX;
643 __xdata __at (0xDF13) unsigned char CSPY;
644 __xdata __at (0xDF14) unsigned char CSPZ;
645 __xdata __at (0xDF15) unsigned char CSPCTRL;
646 __xdata __at (0xDF16) unsigned char CSPT;
647 __xdata __at (0xDF17) unsigned char RFPWR;
648 #define ADI_RADIO_PD 0x10
649 #define RREG_RADIO_PD 0x08
650 #define RREG_DELAY_MASK 0x07
651 
652 __xdata __at (0xDF20) unsigned char FSMTCH;
653 __xdata __at (0xDF21) unsigned char FSMTCL;
654 __xdata __at (0xDF22) unsigned char MANANDH;
655 __xdata __at (0xDF23) unsigned char MANANDL;
656 __xdata __at (0xDF24) unsigned char MANORH;
657 __xdata __at (0xDF25) unsigned char MANORL;
658 __xdata __at (0xDF26) unsigned char AGCCTRLH;
659 __xdata __at (0xDF27) unsigned char AGCCTRLL;
660 
661 __xdata __at (0xDF39) unsigned char FSMSTATE;
662 __xdata __at (0xDF3A) unsigned char ADCTSTH;
663 __xdata __at (0xDF3B) unsigned char ADCTSTL;
664 __xdata __at (0xDF3C) unsigned char DACTSTH;
665 __xdata __at (0xDF3D) unsigned char DACTSTL;
666 
667 __xdata __at (0xDF43) unsigned char IEEE_ADDR0;
668 __xdata __at (0xDF44) unsigned char IEEE_ADDR1;
669 __xdata __at (0xDF45) unsigned char IEEE_ADDR2;
670 __xdata __at (0xDF46) unsigned char IEEE_ADDR3;
671 __xdata __at (0xDF47) unsigned char IEEE_ADDR4;
672 __xdata __at (0xDF48) unsigned char IEEE_ADDR5;
673 __xdata __at (0xDF49) unsigned char IEEE_ADDR6;
674 __xdata __at (0xDF4A) unsigned char IEEE_ADDR7;
675 __xdata __at (0xDF4B) unsigned char PANIDH;
676 __xdata __at (0xDF4C) unsigned char PANIDL;
677 __xdata __at (0xDF4D) unsigned char SHORTADDRH;
678 __xdata __at (0xDF4E) unsigned char SHORTADDRL;
679 __xdata __at (0xDF4F) unsigned char IOCFG0;
680 __xdata __at (0xDF50) unsigned char IOCFG1;
681 __xdata __at (0xDF51) unsigned char IOCFG2;
682 __xdata __at (0xDF52) unsigned char IOCFG3;
683 __xdata __at (0xDF53) unsigned char RXFIFOCNT;
684 __xdata __at (0xDF54) unsigned char FSMTC1;
685 #define ABORTRX_ON_SRXON 0x20
686 #define RX_INTERRUPTED 0x10
687 #define AUTO_TX2RX_OFF 0x08
688 #define RX2RX_TIME_OFF 0x04
689 #define PENDING_OR 0x02
690 #define ACCEPT_ACKPKT 0x01
691 
692 __xdata __at (0xDF60) unsigned char CHVER;
693 __xdata __at (0xDF61) unsigned char CHIPID;
694 __xdata __at (0xDF62) unsigned char RFSTATUS;
695 #define TX_ACTIVE 0x10
696 #define FIFO 0x08
697 #define FIFOP 0x04
698 #define SFD 0x02
699 #define CCA 0x01
700 
701 __xdata __at (0xDFC1) unsigned char U0BUF_SHADOW;
702 
703 __xdata __at (0xDFD9) unsigned char RFD_SHADOW;
704 
705 __xdata __at (0xDFF9) unsigned char U1BUF_SHADOW;
706 
707 __xdata __at (0xDFBA) unsigned int ADC_SHADOW;
708 
709 #endif /*REG_CC2430*/
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